1. Field of the Invention
The present invention relates to a method of measuring a pixel current in a display device in which pixel data for display is written into each pixel arranged in matrix.
2. Description of the Related Art
FIG. 1 illustrates a basic circuit configuration of a pixel (sub-pixel in a color panel) in an active matrix type organic electroluminescence (EL) display device. FIG. 2 illustrates an exemplary configuration of a display panel, and signals input thereto.
While keeping a horizontally-extending gate line (Gate) at high level to turn ON a selection thin film transistor (TFT) 2, a data signal having a voltage corresponding to display luminance is superimposed on a vertically-extending data line (Data), to thereby accumulate the data signal into a storage capacitor C. The storage capacitor C allows a drive TFT 1 to supply a drive current corresponding to the data signal to an organic EL element 3, and the organic EL element 3 emits light.
Here, the emission amount of the organic EL element and its current have a substantially proportional relationship. Generally, a voltage (Vth) at which a drain current starts to flow near the black level of an image is applied between a gate of the drive TFT 1 and PVdd. As an amplitude of the image signal, an amplitude which results in predetermined luminance near the white level is applied.
As illustrated in FIG. 2, the panel has pixels 6 arranged in matrix, in which the gate lines Gate extend from a gate driver 4 and are disposed for each row of the pixels 6. The gate lines Gate for lines to write data signals are sequentially changed to the high level and the respective selection TFTs 2 are turned ON. The data lines Data, on the other hand, extend from a source driver 5 and are disposed for each column of the pixels, and the data signals of the corresponding pixels 6 are sequentially superimposed on the data lines Data. To perform this operation, the gate driver and the source driver are supplied as necessary with an image data signal, horizontal and vertical synchronization signals, a pixel clock, and other drive signals.
FIG. 3 illustrates a relation of a CV current (corresponding to luminance) flowing through the organic EL element 3 with respect to a data (Data) voltage of the drive TFT 1 (voltage of the data signal on the data line Data). The data signal is determined so that Vb is applied as the black level voltage and Vw is applied as the white level voltage, to thereby enable appropriate gradation control on the organic EL element 3.
A current flowing when the pixel is driven at a given data voltage is dependent on the characteristics of the drive TFT 1, such as the voltage Vth and the slope of the V-I curve (μ). Accordingly, luminance unevenness occurs if the characteristics of Vth and a fluctuate among the drive TFTs 1 in the panel. In order to correct the luminance unevenness, it is necessary to input a data voltage for obtaining the same luminance with the same input signal value to each pixel. For that reason, one or a predetermined number of pixels in the panel are lit at different signal levels, and the V-I curve of the TFT is determined based on panel currents at the respective signal levels (see Japanese Patent Application Laid-open Nos. 2004-264793 and 2005-284172).
The current flowing in one pixel, which depends on the efficiency of the organic EL element and the pixel density, is usually several μA or less even for light emission at the maximum available luminance. It is therefore necessary to measure a current of 1 μA or less especially in determining fluctuations in current value near black. Accordingly, intruding noise from outside the panel and noise from the drive circuitry inside the panel may cause the deterioration in measurement accuracy. As a countermeasure, in Japanese Patent Application Laid-open No. 2008-098057, a PVDD current and a CV current are measured at a time and added together so as to remove common-mode noise.
By the way, the plurality of pixels 6 use a common line for supplying power PVdd to a source of the drive TFT 1, and hence, if resistive components due to wiring are present, a source voltage of the drive TFT 1 for driving the organic EL element 3 varies depending on the amount of current flowing in other pixels 6, though the resistive components are omitted in the circuits of FIGS. 1 and 2. If the source voltage of the drive TFT 1 drops while the selection TFT 2 is being turned ON to write the data voltage into the storage capacitor C, an absolute value of Vgs of the drive TFT 1 becomes small. As a result, the current of the drive TFT 1 reduces and the current of the organic EL element 3 also reduces to lower the emission luminance.
In order to solve the problem, Japanese Patent Application Laid-open No. 2009-258301 discloses the configuration as illustrated in FIG. 4, in which two kinds of vertical PVDD power supply lines, that is, a power supply line PVDDa for pixel lighting and a power supply line PVDDb for pixel data writing are provided, and a switch 8 switches the voltage source of a horizontal PVDD line for supplying the PVDD voltage to the pixels 6 in the corresponding horizontal lines. The switching of the switch 8 provided for each horizontal line is controlled by a control signal Ctl supplied from a PVDD line selection circuit 7.
FIG. 4 is a diagram illustrating three columns (n+2 to n) of pixels 6 in four horizontal lines (m to m+3), and FIG. 5 illustrates its overall configuration focusing on the power supply lines (vertical PVDD lines PVDDa and PVDDb and the horizontal PVDD lines). Note that, the voltages of the vertical PVDD lines PVDDa and PVDDb are referred to as PVDDa and PVDDb, respectively.
Here, the PVDD line selection circuit 7 and the switch 8 for PVDD may be formed of a TFT or may employ an IC chip provided with such a function. In normal usage, during lighting, the switches 8 are turned to the “a” side so that power may be supplied from the vertical PVDD line PVDDa. In writing a data voltage, the corresponding switch 8 is turned to the “b” side so that power may be supplied from the vertical PVDD line PVDDb having a voltage sufficiently lower than the lighting voltage on the vertical PVDD line PVDDa. In other words, a pixel current is reduced during the data voltage writing so as to prevent voltage drop in the PVDD line. FIG. 4 is a diagram illustrating a state of writing pixel data in the horizontal line m+1, in which all the switches 8 of the other horizontal PVDD lines with the omitted part included are turned to the “a” side.
FIG. 6 illustrates timing relations between the gate line Gate and the control signal Ctl. A vertical synchronization signal VD is changed to H level every frame. In each frame, the gate signal Gate and the control signal Ctl are sequentially turned ON every horizontal line, to thereby write the data signal into the corresponding pixel while the power supply voltage is being supplied from the vertical PVDD line PVDDb.
As illustrated in FIG. 7, the switch 8 may be provided every plurality of horizontal PVDD lines. FIG. 7 is a diagram illustrating three columns of pixels in four lines in the case where the switch 8 is provided every four horizontal PVDD lines, and FIG. 8 illustrates its overall configuration focusing on the power supply lines. When pixel data is written, the switch 8 for a group to which the pixel to be written belongs is turned to the “b” side so that power may be supplied from the vertical PVDD line PVDDb, and at the same time, the gate selection line Gate on the line to which the pixel to be measured belongs is changed to the high level.
The data voltage is written line by line in order from the upper part of the screen, and hence in FIG. 7, the gate lines Gatem to Gatem+3 are sequentially changed to the high level while the switch 8 is turned to the “b” side. When the writing on the horizontal lines in the group is completed, the switch 8 is switched to the “a” side, and the horizontal PVDD lines in the next group of the lines m+4 to m+7 are connected to PVDDb by another corresponding switch 8. FIG. 9 illustrates a wiring example of the power supply lines in the case where the switches 8 are provided on both sides.
In a compact panel with fewer pixels, leakage currents from other pixels are small, and a capacitive component of the PVDD line, which affects the measurement speed, is also small. Therefore, as in Japanese Patent Application Laid-open No. 2008-098057 described above, it is possible to measure a current at a PVDD terminal by supplying a current to only one pixel while connecting PVdd in all the pixels. However, in a large-sized panel with more pixels, a total amount of noise due to leakage currents from OFF pixels other than the pixel to be measured becomes large to lower the measurement accuracy. Further, there is another problem that the pixel current cannot be measured at high speed because of the influence of time constant due to the capacitive component of the PVDD line.
Meanwhile, a large panel with more pixels has large current consumption and a long PVDD line, and hence the voltage drop in the PVDD line is a serious issue and it is desired to separate the PVDD line into the one for pixel data writing and the one for light emission as in Japanese Patent Application Laid-open No. 2009-258301 described above.
In this case, a preferred manner of measuring a pixel current is such that only the switch for a group of the PVDD lines to which the pixel to be measured belongs is brought into a connected state to apply a voltage thereto and measure the pixel current. In this manner, capacitive components on the PVDD lines in other groups can be eliminated, and leakage currents from the pixels in the other groups can also be eliminated.
However, if PVdd in the pixels other than the group including the pixel to be measured is disconnected during the measurement, amounts and waveforms of intruding noise are considerably different for PVDD and CV. Therefore, in the method of Japanese Patent Application Laid-open No. 2008-098057 assuming that intruding common-mode noise (intruding noise from outside the panel and noise from the drive circuits inside the panel) is not so different for PVDD and CV, it is difficult to remove the common-mode noise.